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Cellular Automata(CA) with simple, regular, modular and
cascadable structures, which the VLSI design community prefer, was
made an alternative proposal of LFSRs. Pseudorandom sequences were
produced by generators which accompany several LFSRs joined by nonlinear
functions or irregular clocking techniques. Clock-Controlled Shrinking
Generators(CCSGs) are a class of clock-controlled sequence generators.
Clock-controlled LFSRs have become important building blocks
for keystream generators in stream cipher applications, because they are
known to produce sequences of long period and high linear complexity.
In this paper, we propose a method of modelling linear CA with the
minimum stage corresponding to CCSGs based on LFSR using the Cho
et al.'s synthesis algorithm.